Programmable Logic Design

Celerity supports the design, simulation and validation of programmable logic using hardware description languages (HDL). Designs range from simple “glue” CPLD’s to complex, modular FPGA design with embedded 3rd party cores.

Functionality, timing and constraints are fully simulated using test benches and simulation software. The design is then fitted and routed into the customers’ targeted device. JTAG and Boundary Scan programming files are delivered along with programming instructions.

Conversions of FPGA’s to low cost, high volume ASIC’s are also supported by Celerity.

Other Services

Celerity also provides the following services:

• Software based diagnostics and Built in Self Test
• Board Support Package (BSP) development